`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2023/03/31 15:41:06
// Design Name: 
// Module Name: register_file
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module register_file(
    input           clk,
    input           rst_n,

    input           en1,
    input           we1,
    input   [6:0]   addr1,
    input   [95:0]  din1,
    output  reg [95:0]  dout1,
    input           en2,
    input           we2,
    input   [6:0]   addr2,
    input   [95:0]  din2,
    output  reg [95:0]  dout2,
    input           en3,
    input           we3,
    input   [7:0]   addr3,
    input   [95:0]  din3,
    output  reg [95:0]  dout3
    // input           en4,
    // input           we4,
    // input   [7:0]   addr4,
    // input   [95:0]  din4,
    // output  [95:0]  dout4

);

    integer i;
    (*ram_style="block"*)reg [95:0]  register   [256-1:0];

    always @(posedge clk or negedge rst_n)begin
    if(rst_n == 1'b0)begin
        for(i = 0; i < 256; i = i + 1)begin
            register[i] = 0;						//存储器初始化
        end
    end
    if(we1 == 1'b1 && en1 == 1'b1)			//a写入，给定一个addr值，写入一个数据进存储器
        register[addr1] <= din1;
    if(we2 == 1'b1 && en2 == 1'b1)			//b写入
        register[addr2] <= din2;
    if(we3 == 1'b1 && en3 == 1'b1)			//b写入
        register[addr3] <= din3;
    end

    always @(posedge clk or negedge rst_n)begin
    if(rst_n == 1'b0)begin							//输出端口初始化
        dout1 <= 0;
        dout2 <= 0;
        dout3 <= 0;
    end
    if(we1 == 1'b0 && en1 == 1'b1)begin		
        dout1 <= register[addr1];					//a读出
        dout2 <= dout2;
        dout3 <= dout3;
    end
    if(we2 == 1'b0 && en2 == 1'b1)begin
        dout2 <= register[addr2];					//b读出
        dout1 <= dout1;
        dout3 <= dout3;
    end
    if(we3 == 1'b0 && en3 == 1'b1)begin
        dout3 <= register[addr3];					//b读出
        dout1 <= dout1;
        dout2 <= dout2;
    end
    else begin
        dout1 <= dout1;
        dout2 <= dout2;
        dout3 <= dout3;
    end
end



endmodule

